1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method for fabricating the same.
2. Description of the Related Art
Electrically Programmable Read Only Memory (EPROM) and Electrically Erasable Programmable Read Only Memory (EEPROM) are widely used as non-volatile semiconductor memory devices. FIG. 11 shows a cross sectional view of a part of a flash type EEPROM of the prior art. Each memory cell transistor of the EEPROM has a channel region (p-type diffusion layer) 2, n-type drain region 3 and source region 4 formed in a p-type silicon substrate 1. Further, each memory cell transistor has a control gate electrode 8 formed on the silicon substrate 1 and a floating gate electrode 9 formed on the control gate electrode 8. A first gate insulation film 5 is provided between the floating gate electrode 9 and the silicon substrate 1, and a second gate insulation film 6 is provided between the floating gate electrode 9 and the control gate electrode 8. These electrodes 8 and 9 are covered by a silicon oxide film 10. Bit lines 12 run over the silicon oxide film 10 so as to interconnect the drain region 3 with drain regions of the other transistors via contact holes provided in the silicon oxide film 10.
While FIG. 11 shows a non-volatile semiconductor memory cell of the non-volatile semiconductor memory device, in fact there exist a large number of memory cells on the silicon substrate 1. The memory cells are electrically isolated from each other by an element isolation film 15 such as LOCOS (Local Oxidation) formed in a prescribed region of the silicon substrate 1.
Storage of information in the non-volatile semiconductor memory device is achieved by storing/unstoring a positive or negative charge in the floating gate electrode 9. Because the positive or negative charge stored in the floating gate electrode 9 affect the threshold voltage (Vt) of the transistor of the memory cell, stored information can be read out by detecting the drain current of the transistor.
The prior art described above has problems which are described below.
When injecting or releasing the positive or negative charge to or from the floating gate electrode 9, relatively high voltages are applied to the control gate electrode 8 and the bit lines 12. Therefore a structure of word line (control gate electrode 8)/element isolation film 15/silicon substrate 1 functions as a parasitic MOS structure formed between adjacent memory cells and, as a result, a conduction channel may be formed between the adjacent memory cells. Such a conduction channel breaks the isolation between the adjacent memory cells. In order to maintain the element isolation, it is necessary to make the element isolation film 15 thicker and wider, which is incompatible with the aim of achieving a large scale integration of memory transistors.
Also it is generally necessary to increase the operating current (for example the drain current) of the transistor to increase the speed of reading data. However, reduction of the channel width of the transistor for the purpose of scaling down the size of the semiconductor memory leads to a decrease in the operating current.
Further, in the constitution as described above, the inversion threshold voltages of memory cell transistors are likely to fluctuate due to the fluctuation of the amount of the stored charges in the floating gate electrode. For this reason, it is necessary to write all data in batch before making an erasing operation (or a writing operation), or repeating the erasing operation and checking of the threshold voltage (Vt). This checking operations are called as "verifying operations" and increase the time taken in erasure or writing.